Date: Mon, 11 Nov 1996 21:04:34 GMT
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<title>Class projects</title>
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<h2>Class projects</h2>
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<b>VLSI Systems Design 
<!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><!WA0><a href="http://www.cs.wisc.edu/~pubs/grad-guidebook/node9.html#cs755">(CS 755)</a>
</b>
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Co-designed and simulated a chip implementing a directory controller for 
a shared-memory multiprocessor.  The design was performed at gate and 
standard-cell level, using the M gate-level-expression language and the 
Autologic logic-synthesis tool suite from Mentor Graphics.<br>
<cite>
(With
<!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><!WA1><a href="http://www.cs.wisc.edu/~shubu/shubu.html">Shubu Mukherjee</a>,
<!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><!WA2><a href="http://www.cs.wisc.edu/~subbarao/subbarao.html">Subbarao Palacharla</a>,
and
<!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><!WA3><a href="http://www.cs.wisc.edu/~stever/stever.html">Steve Reinhardt</a>)
</cite>
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<b>Uniprocessor Computer Architecture 
<!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><!WA4><a href="http://www.cs.wisc.edu/~pubs/grad-guidebook/node9.html#cs752">(CS 752)</a>
</b>
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Evaluated the efficacy of the Named-State Register File (NSRF) from MIT.
Essentially a cache for
registers belonging to many different contexts, the NSRF was designed for
a multithreaded parallel computer, replacing the fixed number of separate
register files present in a typical multithreaded architecture.  In this
project, we examined the utility of the NSRF for a <cite>uniprocessor</cite>
running several unrelated contexts.  Our simulation strategy 
involved extracting the register references from a number of running
programs and passing the references to a cache simulator.  Evaluation 
involved varying the number of contexts, time-slice length, NSRF size, 
and NSRF associativity, and determining the resultant miss ratios.
<cite>
(With
<!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><!WA5><a href="http://www.cs.wisc.edu/~jignesh/jignesh.html">Jignesh Patel</a>)
</cite>
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<b>Parallel Computer Architecture
<!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><!WA6><a href="http://www.cs.wisc.edu/~pubs/grad-guidebook/node9.html#cs757">(CS 757)</a>
</b>
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Measured the performance of various implementations of software 
synchronization methods both for shared-memory multiprocessors (locks 
and barriers) and for message-passing multicomputers (barriers only).
Evaluation involved measuring the performance of synchronization kernels
on a Sequent Symmetry multiprocessor and on an Intel iPSC/2 multicomputer.
<cite>
(With Po-Yung Chang)
</cite>
<p>
<b>Parallel Computing and Computational Science 
<!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><!WA7><a href="http://www.cs.wisc.edu/~pubs/grad-guidebook/node9.html#cs838">(CS 838)</a>
</b>
<p>
Parallelized the NAS Parallel Benchmark APPLU, a computational-fluid-
dynamics simulation code, porting it to data-parallel CM-Fortran for the 
CM-5 and porting it to the Sequent Symmetry.  Evaluation involved running
sequential and parallel versions of the code and measuring its speedup 
for varying numbers of processors.
<cite>
(With James Puthukattukaran and Phil Stephenson)
</cite>
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<b>Database Design
<!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><!WA8><a href="http://www.cs.wisc.edu/~pubs/grad-guidebook/node9.html#cs564">(CS 564)</a>
</b>
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Implemented major components of a database management system given a 
specification; components implemented included a paged-file layer, an 
unordered-file layer, an access-methods layer (B-tree implementation), 
and a front-end layer that interprets SQL commands.
<cite>
(With Olubunmi Odumade)
</cite>
<p>
<!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><!WA9><a href="http://www.cs.wisc.edu/~hyder/hyder.html">Back to my home page</a>
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<cite> Last updated: October 15, 1995</cite>
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